GaiaFTCL Lithography — Silicon Cell (M8 substrate)

FortressAI Research Institute | Norwich, Connecticut

Patents: USPTO 19/460,960 | USPTO 19/096,071 — © 2026 Richard Gillespie

Mirror: Tracks the GitHub Wiki page. Prefer main blob links below for authoritative specs.

Media — walkthrough (poster → MP4)


Pages player: gaiaFTCL#lithography · Wiki video page

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1. What this cell is

GaiaLithography is the physical silicon cell in the FoT8D repository: it specifies how the M8 substrate is designed, qualified, and tape-out–governed — PDK binding, chiplet IP, Torsion Interposer, HMMU (hardware isolation between S4 and C4 memory views), LithoPrimitive (128-byte fab events), and the nine-state lithography state machine from IDLE through TAPEOUT_LOCKED / SHIPPED.

Sibling cells:

Canonical README: cells/lithography/README.md

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2. vQbit is one part — not the whole cell

The vQbit model (entropy delta across M⁸, vQbitPrimitive, Xvqbit ISA extensions) is the measurement / instruction contract shared with Fusion and Health. GaiaLithography additionally owns PDK/floorplan/signoff, package integration, HMMU, and GAMP 5 lifecycle — i.e. the full tape-out story, including leading-edge (“1 nm class”) PDK targets (e.g. N3P, N2) as design qualification space, not a single shorthand for “only vQbit.”

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3. IQ / OQ / PQ

Single-page summary: cells/lithography/docs/IQ_OQ_PQ_LITHOGRAPHY_CELL.md

Full GAMP map: cells/lithography/docs/GAMP5_LIFECYCLE.md

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4. State machine

IDLE → MOORED → PDK_BOUND → FLOORPLAN → ROUTED → SIGNOFF → TAPEOUT_LOCKED → SHIPPED
                                                      └──────→ MASK_REJECTED
         └──→ HMMU_BREACH

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*Controlled item CI-M8-001.*